The invention relates generally to integrated circuit packages and, more particularly, to an apparatus and method of fabricating a package having a reduced thickness.
Chip scale packages or integrated circuit (IC) packages are typically fabricated having a number of dies or chips encapsulated within an embedding compound. A laminate re-distribution layer covers the active side of each of the plurality of dies and typically comprises a dielectric laminate material, such as Kapton, affixed to the plurality of dies using a layer of adhesive. The plurality of dies are electrically connected to an input/output system by way of metal interconnects routed through a plurality of additional laminate re-distribution layers. Each additional re-distribution layer increases the overall thickness of the IC package.
Advancements in IC packaging requirements pose challenges to the existing embedded chip build-up process. That is, it is desired in many current embedded chip packages to have an increased number of re-distribution layers, with eight or more re-distribution layers being common. The advancements are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. Thus, as ICs become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminate-based ball grid array (BGA) packaging, to chip-scale packaging (CSP), to flipchip packages, and to embedded chip build-up packaging. However, these stacking methods typically result in an unacceptably thick package height.
Furthermore, due to the small size and complexity of IC packages, the process for fabricating IC packages is typically expensive and time consuming. The fabrication process typically begins by placing the plurality of dies or chips active-side down onto a sacrificial layer, which serves to position and support the plurality of dies during the encapsulation process. Once the encapsulant has cured, the sacrificial layer is removed.
Accordingly, there is a need for a simplified method for fabricating IC packages. There is a further need for a method for fabricating more complex and intricate IC packages while minimizing the thickness of the chip scale package.
It would therefore be desirable to have an apparatus and streamlined method of fabricating a complex IC package having a reduced thickness.